May 12, 2026 Melissa Kashouh

d-Matrix – Hardware Qualification Engineer, Senior Staff

  • Anywhere

● TALENT ONE MARKET INTELLIGENCE: D-MATRIX

πŸ”₯ TALENT LIQUIDITY:
Extremely tight. The intersection of AI-specific ASIC knowledge and high-volume reliability engineering is a niche with a 1:30 supply-to-demand ratio.

πŸ“ˆ ALPHA SIGNAL:
This role is the ‘Gatekeeper’ of the company’s revenue. By owning the qualification strategy, you are de-risking the product launch, which directly correlates to your equity value and long-term financial stability.

EST. COMPENSATION
$220k – $280k Base + Significant Equity/RSUs
SECTOR HEAT
88.0/100
CANDIDATE PROTOCOL: Focus your narrative on ‘Zero-Failure’ deployment. If you have experience taking an ASIC from EVT to mass-scale production in a 24/7 data center environment, you are the primary asset.

Official Role Description: d-Matrix

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible.Β Our culture is one of respect and collaboration.We value humility and believe in direct communication.Β Our team is inclusive, and our differing perspectives allow for better solutions.Β We are seeking individuals passionate about tackling challenges and are driven by execution.Β  Ready to come find your playground? Together, we can help shape the endless possibilities of AI.Β Hardware Qualification Engineer, Senior Staff Location: Santa Clara, CA (Onsite/Hybrid)About the RoleAs a Hardware Qualification Engineer, Senior Staff, you will be the final gatekeeper of quality and reliability for our next-generation AI compute platforms. This is a high-impact, technical leadership role responsible for defining the qualification strategies that ensure our hardwareβ€”from ASIC substrates to Rack scale systems β€” can withstand the rigorous demands of 24/7 data center environments.You will bridge the gap between design and mass production, ensuring that “cutting edge” doesn’t mean “fragile.”Key ResponsibilitiesQualification Strategy: Define and execute comprehensive HW qualification plans (EVT/DVT/PVT) for complex AI accelerator systems, including PCIe cards OAM modules and chassis systems.Stress & Reliability Testing: Lead the implementation of HALT/HASS, thermal cycling, humidity, and vibration testing to identify marginalities in high-power ASIC designs.Signal & Power Integrity Validation: Provide senior-level oversight for the validation of high-speed SerDes (112G/224G/PCIe), LPDDR, CoWOS designs, and complex PDN (Power Delivery Network) transients.Failure Analysis (FA): Drive root-cause analysis for complex system-level failures, utilizing tools like X-ray, CT scan, and SEM/EDX to distinguish between design flaws, manufacturing defects, and material fatigue.Interconnect Reliability: Specifically oversee the qualification of high-bandwidth interconnects (NVLink/UALink equivalents) and PCIe Gen5/6 link stability.Cross-Functional Influence: Work directly with Design, Thermal, and Firmware teams to implement hardware fixes based on qualification data.Vendor Management: Partner with CMs (Contract Manufacturers) and JDMs to align on test methodologies and production outgoing quality limits (OQL).Required QualificationsEducation: BS/MS in Electrical Engineering, Mechanical Engineering, or Reliability Engineering.Experience: 12+ years in hardware qualification or reliability, specifically with high-performance computing (HPC), servers, or networking hardware.Technical Depth: Mastery of JEDEC, IPC, and Telcordia standards for hardware reliability.Diagnostic Skills: Expert-level experience with high-speed oscilloscopes, logic analyzers, and environmental chambers.Statistical Proficiency: Strong command of statistical methods (Weibull analysis, DOE, and JMP/Minitab) to predict product life cycles and failure rates.Preferred SkillsExperience qualifying Air and Liquid Cooling components (CDUs, cold plates, leak detection) for high-TDP AI systems.Background in ASIC/Package-level reliability, including electromigration and Thermal Stress Analysis.Familiarity with Python or LabVIEW for automating complex test sequences.The “d-Matrix” EdgeWe don’t just test; we innovate. You will be working on a unique chiplet-based architecture where traditional qualification boundaries are blurred. You’ll have the opportunity to build a world-class reliability lab from the ground up and set the standard for how Digital In-Memory Computing (DIMC) is validated.Equal Opportunity Employment Policyd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Melissa Kashouh

Founder of Talent One I help enterprise leaders and investors forecast hiring surges, talent shortages, and market friction up to six weeks in advance using our patent-pending predictive intelligence platform. As the founder of Talent One AI (the intelligence layer of The Talent One), I built a system that turns lagging recruiting data into actionable foresight β€” helping companies reduce technical debt, protect employer brand, and hire ahead of the curve. Based in Providence, Rhode Island.
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